The present invention relates, in general, to automated digital test systems. More particularly, the invention relates to a method and apparatus for transferring data between a multi-channel tester and a logic circuit having more circuit terminals, or pins, than the number of test channels available.
Testing logic circuits, and specifically integrated circuits, is of prime importance to electronic circuit manufacturers so as to identify defective units before they are assembled and used. It is desirable to test integrated circuits before and after the circuits are packaged. The electronic industry is moving towards shrinking dimensions and increasing complexity of electronic circuits, which increases the number of pins needed to communicate with the circuits. As circuits become more complex, it becomes difficult or impossible to test the circuits on existing equipment. It is becoming important for testers to be able to support circuits with several hundred to more than one thousand terminals, while at the same time decreasing the cost of the test apparatus. Accordingly, methods for expanding the number of terminals that a single test channel can support have been developed to meet demands of new circuits.
Another trend in integrated circuit manufacture is towards application specific and customer designed circuits, resulting in a large variety of circuits, with various design rules, that must be tested. These added complexities can make the cost of testing a circuit account for a significant portion of the finished circuit cost. Also, testing has placed limitations on circuit design rules which often compromise circuit performance. Test apparatus must be increasingly flexible and able to support a wide variety of circuits with a minimum number of limitations placed on design of the circuit.
One area of particular interest is transferring test signals between the tester and the circuit under test. Each channel of a tester typically has multiple force and measure circuits, used for passing serial stimulus data from the tester to the circuit under test, and serial response data from the circuit under test to the tester. A pattern of stimulus signals, or stimulus vectors, is stored in a mass storage unit associated with the tester. Each terminal of the circuit under test is associated with a driver, used to force a logic signal on the terminal, and a comparator, used to detect a response voltage on the terminal, and output a response vector to the tester. The tester passes the stimulus vector to the force and measure circuit which control the drivers and comparators. In this manner, the stimulus vector is applied to the circuit under test and the response vector is recorded from the circuit under test. For circuits with a large number of pins, however, replication of force and measure circuits for each terminal becomes expensive. Also, new circuits with higher pin counts are developed more quickly than testers to evaluate them, thus manufacturers find themselves with test equipment having fewer test channels than the number of circuit terminals.
One solution to this problem was to include test circuitry as a part of the circuit under test. Several methods were used, but each is similar in that they required additional logic devices in the circuit and slowed circuit performance. One popular method, called boundary scan, comprised a chain of shift register latches coupled between each terminal of the logic circuit. In this method, the stimulus vector was passed from one test channel to all of the terminals of the circuit by shifting the vector along the chain of shift register latches. Upon receiving a strobe pulse from the tester, the shift register latches applied the stimulus vector to the circuit under test. In a like manner, the response vector was loaded into the shift register chain and shifted out of the circuit under test to the tester. Boundary scan techniques used only four terminals: stimulus vector in, response vector out, clock, and strobe. Test time using boundary scan, however, was multiplied by the number of terminals in the chain. Thus, for a 100 pin circuit, 100 clock pulses were required to transfer the stimulus vector to the circuit under test, and 100 clock pulses were required to transfer the response vector from the circuit under test to the tester, resulting in significant increase in test time for devices with large numbers of terminals. In addition, boundary scan circuitry added delay time to every input and output from the logic circuit when the logic circuit was in use. Finally, the boundary scan circuitry added up to 25% more chip area to a circuit, increasing cost of the logic circuit.
Another solution was to upgrade the tester to support more circuit terminals. This required test channels be multiplexed to support more than one terminal, or new equipment be purchased. Previous multiplexing methods were too slow and did not completely test the logic circuit. New equipment with more test channels is increasingly expensive, and usually not yet available when the manufacturer first produces circuits. Thus, there exists a need for a test apparatus that supports more than one circuit terminal with each test channel, as well as maintaining flexibility to fully test a variety of logic circuits, without imposing restrictions and limitations on the circuit to be tested.
Accordingly, it is an object of the present invention to provide a method and apparatus for transferring data between a tester and a logic circuit under test using a minimum number of components.
It is a further object of the present invention to provide a method and apparatus for transferring data between a tester and a logic circuit under test which is of minimal cost.
It is a further object of the present invention to provide a method and apparatus for transferring data between a tester and a logic circuit under test which can support more than one circuit terminal per test channel.
It is a further object of the present invention to provide a method and apparatus for transferring data between a tester and a logic circuit under test which allows a wide variety of logic circuits to be tested.